| Regularizing activation distribution for training binarized deep networks R Ding, TW Chin, Z Liu, D Marculescu Proceedings of the IEEE/CVF conference on computer vision and pattern …, 2019 | 165 | 2019 |
| Quantized deep neural networks for energy efficient hardware-based inference R Ding, Z Liu, RDS Blanton, D Marculescu 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 1-8, 2018 | 55 | 2018 |
| Lightnn: Filling the gap between conventional deep neural networks and binarized networks R Ding, Z Liu, R Shi, D Marculescu, RD Blanton Proceedings of the on Great Lakes Symposium on VLSI 2017, 35-40, 2017 | 48 | 2017 |
| Flightnns: Lightweight quantized deep neural networks for fast and accurate inference R Ding, Z Liu, TW Chin, D Marculescu, RD Blanton Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 31 | 2019 |
| Characterization of locked sequential circuits via ATPG D Duvalsaint, Z Liu, A Ravikumar, RD Blanton 2019 IEEE International Test Conference in Asia (ITC-Asia), 97-102, 2019 | 27 | 2019 |
| Design reflection for optimal test-chip implementation RDS Blanton, B Niewenhuis, ZD Liu 2015 IEEE International Test Conference (ITC), 1-10, 2015 | 24 | 2015 |
| Lightening the load with highly accurate storage-and energy-efficient lightnns R Ding, Z Liu, RD Blanton, D Marculescu ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (3), 1-24, 2018 | 22 | 2018 |
| Achieving 100% cell-aware coverage by design Z Liu, B Niewenhuis, S Mittal, RD Blanton 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 109-114, 2016 | 16 | 2016 |
| Test chip design for optimal cell-aware diagnosability S Mittal, Z Liu, B Niewenhuis, RDS Blanton 2016 IEEE International Test Conference (ITC), 1-8, 2016 | 14 | 2016 |
| Front-end layout reflection for test chip design Z Liu, P Fynan, RD Blanton 2017 IEEE International Test Conference (ITC), 1-10, 2017 | 12 | 2017 |
| Logic characterization vehicle design reflection via layout rewiring P Fynan, Z Liu, B Niewenhuis, S Mittal, M Strajwas, RDS Blanton 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 10 | 2016 |
| Improving test chip design efficiency via machine learning Z Liu, Q Huang, C Fang, RD Blanton 2019 IEEE International Test Conference (ITC), 1-10, 2019 | 9 | 2019 |
| SACSR: A low power BIST method for sequential circuits S Lei Academic Journal of Xi'an Jiaotong University, 155-159, 2008 | 9 | 2008 |
| CompactNet: High accuracy deep neural network optimized for on-chip implementation A Goel, Z Liu, RD Blanton 2018 IEEE International Conference on Big Data (Big Data), 4723-4729, 2018 | 7 | 2018 |
| Back-end layout reflection for test chip design Z Liu, RD Blanton 2018 IEEE 36th International Conference on Computer Design (ICCD), 456-463, 2018 | 7 | 2018 |
| Flexible, lightweight quantized deep neural networks R Ding, Z Liu, TW Chin, D Marculescu, RD Blanton US Patent 11,521,074, 2022 | 2 | 2022 |
| IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design Q Huang, C Fang, Z Liu, R Ding, RDS Blanton 2019 IEEE 37th International Conference on Computer Design (ICCD), 11-19, 2019 | 2 | 2019 |
| A unified solution to reduce test power and test volume for Test-per-scan schemes S Lei, Z Wang, Z Liu, F Liang IEICE Electronics Express 7 (18), 1364-1369, 2010 | 2 | 2010 |
| Efficient test chip design via smart computation C Fang, Q Huang, Z Liu, R Ding, RD Blanton ACM Transactions on Design Automation of Electronic Systems 28 (2), 1-31, 2023 | 1 | 2023 |
| High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips Z Liu, RDS Blanton 2020 IEEE International Test Conference (ITC), 1-10, 2020 | 1 | 2020 |
Ruizhou DingCarnegie Mellon UniversityVerified email at andrew.cmu.edu
