A+ 70-dBm IIP3 electrical-balance duplexer for highly integrated tunable front-ends B Van Liempd, B Hershberg, S Ariumi, K Raczkowski, KF Bink, ...
IEEE Transactions on Microwave Theory and Techniques 64 (12), 4274-4286, 2016
126 2016 A 0.9 V 0.4–6 GHz harmonic recombination SDR receiver in 28 nm CMOS with HR3/HR5 and IIP2 calibration B van Liempd, J Borremans, E Martens, S Cha, H Suys, B Verbruggen, ...
IEEE Journal of Solid-State Circuits 49 (8), 1815-1826, 2014
125 2014 A single-channel, 600-MS/s, 12-b, ringamp-based pipelined ADC in 28-nm CMOS J Lagos, B Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 54 (2), 403-416, 2018
93 2018 Classification of analog synthesis tools based on their architecture selection mechanisms E Martens, G Gielen
Integration 41 (2), 238-252, 2008
87 2008 A 1-GS/s, 12-b, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers J Lagos, BP Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 54 (3), 646-658, 2019
86 2019 A DTC-based subsampling PLL capable of self-calibrated fractional synthesis and two-point modulation N Markulic, K Raczkowski, E Martens, PE Paro Filho, B Hershberg, ...
IEEE Journal of Solid-State Circuits 51 (12), 3078-3092, 2016
77 2016 RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass E Martens, A Bourdoux, A Couvreur, R Fasthuber, P Van Wesemael, ...
IEEE Journal of Solid-State Circuits 47 (4), 990-1002, 2012
68 2012 A compact quad-shank CMOS neural probe with 5,120 addressable recording sites and 384 fully differential parallel channels S Wang, SK Garakoui, H Chun, DG Salinas, W Sijbers, J Putzeys, ...
IEEE transactions on biomedical circuits and systems 13 (6), 1625-1634, 2019
62 2019 A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation B Verbruggen, J Tsouhlarakis, T Yamamoto, M Iriguchi, E Martens, ...
IEEE Journal of Solid-State Circuits 50 (9), 2002-2011, 2015
49 2015 A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, ringamp-based pipelined-SAR ADC With background calibration and dynamic reference regulation in 16-nm CMOS J Lagos, N Markulić, B Hershberg, D Dermit, M Shrivas, E Martens, ...
IEEE Journal of Solid-State Circuits 57 (4), 1112-1124, 2022
47 2022 3.1 A 3.2 GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion B Hershberg, D Dermit, B van Liempd, E Martens, N Markulic, J Lagos, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 58-60, 2019
46 2019 A 69-dB SNDR 300-MS/s two-time interleaved pipelined SAR ADC in 16-nm CMOS FinFET with capacitive reference stabilization E Martens, B Hershberg, J Craninckx
IEEE Journal of Solid-State Circuits 53 (4), 1161-1171, 2018
46 2018 A 0.9 V low-power 0.4–6GHz linear SDR receiver in 28nm CMOS J Borremans, B van Liempd, E Martens, S Cha, J Craninckx
2013 Symposium on VLSI Circuits, C146-C147, 2013
44 2013 A 4-GS/s 10-ENOB 75-mW ringamp ADC in 16-nm CMOS with background monitoring of distortion B Hershberg, D Dermit, B van Liempd, E Martens, N Markulić, J Lagos, ...
IEEE Journal of Solid-State Circuits 56 (8), 2360-2374, 2021
35 2021 An analytical integration method for the simulation of continuous-time/spl Delta//spl Sigma/modulators GGE Gielen, K Francken, E Martens, M Vogels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2004
35 2004 16.3 A single-channel 5.5 mW 3.3 GS/s 6b fully dynamic pipelined ADC with post-amplification residue generation Z Zheng, L Wei, J Lagos, E Martens, Y Zhu, CH Chan, J Craninckx, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 254-256, 2020
31 2020 A behavioral simulation tool for continuous-time ΔΣ modulators K Francken, M Vogels, E Martens, G Gielen
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided …, 2002
31 2002 A 1-MS/s to 1-GS/s ringamp-based pipelined ADC with fully dynamic reference regulation and stochastic scope-on-chip background monitoring in 16 nm B Hershberg, N Markulić, J Lagos, E Martens, D Dermit, J Craninckx
IEEE Journal of Solid-State Circuits 56 (4), 1227-1240, 2021
30 2021 9.7 a self-calibrated 10mb/s phase modulator with-37.4 db evm based on a 10.1-to-12.4 ghz,-246.6 db-fom, fractional-n subsampling pll N Markulic, K Raczkowski, E Martens, PE Paro Filho, B Hershberg, ...
2016 IEEE International Solid-State Circuits Conference (ISSCC), 176-177, 2016
29 2016 Top-down heterogeneous synthesis of analog and mixed-signal systems E Martens, G Gielen
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
28 2006 
Barend van LiempdManager Hardware Engineering at PharrowtechOverená e-mailová adresa na: pharrowtech.com
