Hideo Fujiwara 藤原秀雄
Hideo Fujiwara 藤原秀雄
Professor Emeritus, NAIST
Verified email at - Homepage
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A neutral netlist of 10 combinational circuits and a targeted translator in FORTRAN
F Brglez, H Fujiwara
IEEE, Proc. Int. Symp. on Circuits and Systems (ISCAS'85), pp. 663-698, 1985
On the acceleration of test generation algorithms
Fujiwara, Shimono
IEEE Transactions on Computers 100 (12), 1137-1144, 1983
Logic Testing and Design for Testability
H Fujiwara
MIT Press, 1985
Lewy bodies contain altered α-synuclein in brains of many familial Alzheimer's disease patients with mutations in presenilin and amyloid precursor protein genes
CF Lippa, H Fujiwara, DMA Mann, B Giasson, M Baba, ML Schmidt, ...
The American journal of pathology 153 (5), 1365-1370, 1998
The complexity of fault detection problems for combinational circuits
H Fujiwara, S Toida
IEEE Transactions on computers 31 (6), 555-560, 1982
A design of programmable logic arrays with universal tests
H Fujiwara, K Kinoshita
Joint Special Issue on Design for Testability, IEEE Trans. on Computers …, 1981
FAN: A Fanout-Oriented Test Pattern Generation Algorithm
H Fujiwara
IEEE International Symposium on Circuits and Systems, 671-674, 1985
A test methodology for interconnect structures of LUT-based FPGAs
H Michinishi, T Yokohira, T Okamoto, T Inoue, H Fujiwara
Proceedings of the Fifth Asian Test Symposium (ATS'96), 68-74, 1996
Implementing a built-in self-test PLA design
R Treuer, H Fujiwara, VK Agarwal
IEEE Design & Test of Computers 2 (2), 37-48, 1985
Universal fault diagnosis for lookup table FPGAs
T Inoue, S Miyazaki, H Fujiwara
IEEE Design & Test of Computers 15 (1), 39-44, 1998
Parity-scan design to reduce the cost of test application
H Fujiwara, A Yamamoto
IEEE transactions on computer-aided design of integrated circuits and …, 1993
Computational complexity of controllability/observability problems for combinational circuits
H Fujiwara
IEEE Transactions on Computers 39 (6), 762-767, 1990
A new PLA design for universal testability
H Fujiwara
IEEE transactions on computers 100 (8), 745-750, 1984
Efficient test solutions for core-based designs
E Larsson
Introduction to Advanced System-on-Chip Test Design and Optimization, 215-251, 2005
SPIRIT: A highly robust combinational test generation algorithm
E Gizdarski, H Fujiwara
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2002
Universal test complexity of field-programmable gate arrays
T Inoue, H Fujiwara, H Michinishi, T Yokohira, T Okamoto
Proceedings of the Fourth Asian Test Symposium, 259-265, 1995
Reconfigured scan forest for test application cost, test data volume, and test power reduction
D Xiang, K Li, J Sun, H Fujiwara
IEEE Transactions on Computers 56 (4), 557-562, 2007
An optimal time expansion model based on combinational ATPG for RT level circuits
T Inoue, T Hosokawa, T Mihara, H Fujiwara
Proceedings Seventh Asian Test Symposium (ATS'98)(Cat. No. 98TB100259), 190-197, 1998
Design for strong testability of RTL data paths to provide complete fault efficiency
H Wada, T Masuzawa, KK Saluja, H Fujiwara
VLSI Design 2000. Wireless and Digital Imaging in the Millennium …, 2000
Easily testable sequential machines with extra inputs
H Fujiwara, Y Nagao, T Sasao, K Kinoshita
IEEE Transactions on Computers 100 (8), 821-826, 1975
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