| A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors C Auth, C Allen, A Blattner, D Bergstrom, M Brazier, M Bost, M Buehler, ... 2012 symposium on VLSI technology (VLSIT), 131-132, 2012 | 1027 | 2012 |
| Intrinsic transistor reliability improvements from 22nm tri-gate technology S Ramey, A Ashutosh, C Auth, J Clifford, M Hattendorf, J Hicks, R James, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 4C. 5.1-4C. 5.5, 2013 | 205 | 2013 |
| BTI reliability of 45 nm high-K+ metal-gate process technology S Pae, M Agostinelli, M Brazier, R Chau, G Dewey, T Ghani, M Hattendorf, ... 2008 IEEE International Reliability Physics Symposium, 352-357, 2008 | 155 | 2008 |
| Self-heat reliability considerations on Intel's 22nm Tri-Gate technology C Prasad, L Jiang, D Singh, M Agostinelli, C Auth, P Bai, T Eiles, J Hicks, ... 2013 IEEE International Reliability Physics Symposium (IRPS), 5D. 1.1-5D. 1.5, 2013 | 122 | 2013 |
| Modeling of multiple-quantum-well solar cells including capture, escape, and recombination of photoexcited carriers in quantum wells SM Ramey, R Khoie IEEE transactions on electron devices 50 (5), 1179-1188, 2003 | 97 | 2003 |
| Transistor aging and reliability in 14nm tri-gate technology S Novak, C Parker, D Becher, M Liu, M Agostinelli, M Chahal, P Packan, ... 2015 IEEE International Reliability Physics Symposium, 2F. 2.1-2F. 2.5, 2015 | 80 | 2015 |
| Reliability studies of a 10nm high-performance and low-power CMOS technology featuring 3rd generation FinFET and 5th generation HK/MG A Rahman, J Dacuna, P Nayak, G Leatherman, S Ramey 2018 IEEE International Reliability Physics Symposium (IRPS), 6F. 4-1-6F. 4-6, 2018 | 73 | 2018 |
| Self-heating in advanced CMOS technologies C Prasad, S Ramey, L Jiang 2017 IEEE International Reliability Physics Symposium (IRPS), 6A-4.1-6A-4.7, 2017 | 68 | 2017 |
| A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors CH Jan, P Bai, J Choi, G Curello, S Jacobs, J Jeong, K Johnson, D Jones, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 60-63, 2005 | 68 | 2005 |
| Frequency and recovery effects in high-κ BTI degradation S Ramey, C Prasad, M Agostinelli, S Pae, S Walstra, S Gupta, J Hicks 2009 IEEE International Reliability Physics Symposium, 1023-1027, 2009 | 57 | 2009 |
| The effective potential in device modeling: the good, the bad and the ugly DK Ferry, S Ramey, L Shifren, R Akis Journal of Computational Electronics 1, 59-65, 2002 | 54 | 2002 |
| Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures C Prasad, M Agostinelli, J Hicks, S Ramey, C Auth, K Mistry, S Natarajan, ... 2014 IEEE International Reliability Physics Symposium, 6A. 5.1-6A. 5.7, 2014 | 53 | 2014 |
| Random charge effects for PMOS NBTI in ultra-small gate area devices M Agostinelli, S Pae, W Yang, C Prasad, D Kencke, S Ramey, E Snyder, ... 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings …, 2005 | 48 | 2005 |
| Modeling of quantum effects in ultrasmall FD-SOI MOSFETs with effective potentials and three-dimensional Monte Carlo SM Ramey, DK Ferry Physica B: Condensed Matter 314 (1-4), 350-353, 2002 | 48 | 2002 |
| Transistor reliability variation correlation to threshold voltage S Ramey, M Chahal, P Nayak, S Novak, C Prasad, J Hicks 2015 IEEE International Reliability Physics Symposium, 3B. 2.1-3B. 2.6, 2015 | 31 | 2015 |
| Dielectric breakdown in a 45 nm high-k/metal gate process technology C Prasad, M Agostinelli, C Auth, M Brazier, R Chau, G Dewey, T Ghani, ... 2008 IEEE International Reliability Physics Symposium, 667-668, 2008 | 29 | 2008 |
| Transistor reliability characterization and comparisons for a 14 nm tri-gate technology optimized for System-on-Chip and foundry platforms C Prasad, KW Park, M Chahal, I Meric, SR Novak, S Ramey, P Bai, ... 2016 IEEE International Reliability Physics Symposium (IRPS), 4B-5-1-4B-5-8, 2016 | 27 | 2016 |
| BTI recovery in 22nm tri-gate technology S Ramey, J Hicks, LS Liyanage, S Novak 2014 IEEE International Reliability Physics Symposium, XT. 2.1-XT. 2.6, 2014 | 27 | 2014 |
| Implementation of surface roughness scattering in Monte Carlo modeling of thin SOI MOSFETs using the effective potential SM Ramey, DK Ferry IEEE Transactions on Nanotechnology 2 (2), 110-114, 2003 | 25 | 2003 |
| Aging model challenges in deeply scaled tri-gate technologies S Ramey, Y Lu, I Meric, S Mudanai, S Novak, C Prasad, J Hicks 2015 IEEE International Integrated Reliability Workshop (IIRW), 56-62, 2015 | 24 | 2015 |
