| Fastgr: Global routing on cpu–gpu with heterogeneous task graph scheduler S Liu, Y Pu, P Liao, H Wu, R Zhang, Z Chen, W Lv, Y Lin, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 31 | 2022 |
| Restructure-tolerant timing prediction via multimodal fusion Z Wang, S Liu, Y Pu, S Chen, TY Ho, B Yu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 18 | 2023 |
| Customized retrieval augmented generation and benchmarking for eda tool documentation qa Y Pu, Z He, T Qiu, H Wu, B Yu arXiv preprint arXiv:2407.15353, 2024 | 7 | 2024 |
| IncreMacro: Incremental Macro Placement Refinement Y Pu, T Chen, Z He, C Bai, H Zheng, Y Lin, B Yu Proceedings of the 2024 International Symposium on Physical Design, 169-176, 2024 | 4 | 2024 |
| Parsgcn: Bridging the gap between emulation partitioning and scheduling Z Wang, W Zhao, Y Pu, L Chen, WWK Thong, W Sheng, TY Ho, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| Neuroselect: Learning to select clauses in sat solvers H Liu, P Xu, Y Pu, L Yin, HL Zhen, M Yuan, TY Ho, B Yu Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 1 | 2024 |
| HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning Y Pu, F Liu, Z He, K Zhu, R Fu, Z Wang, TY Ho, B Yu International Symposium on Physical Design (ISPD’25), 2025 | | 2025 |
| Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment H Wu, H Zheng, Y Pu, B Yu arXiv preprint arXiv:2502.12732, 2025 | | 2025 |
| EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling J Xu, Z He, S Yin, Y Pu, W Yu, B Yu ACM Transactions on Design Automation of Electronic Systems, 2025 | | 2025 |
| Lesyn: Placement-Aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs Y Pu, F Liu, Y Zhang, Z He, Y Lin, KY Chao, B Yu Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | | 2024 |
| Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells Y Zhang, Y Pu, F Liu, P Liao, KY Chao, K Zhu, Y Lin, B Yu Proceedings of the 2024 International Symposium on Physical Design, 161-168, 2024 | | 2024 |
| Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment WU Haoyuan, H Zheng, Y Pu, B Yu The Thirteenth International Conference on Learning Representations, 0 | | |
