Roy Paily
Roy Paily
Professor, Electronics and Electrical Engineering and Centre for Nanotechnology, IIT Guwahati
Verified email at - Homepage
Cited by
Cited by
A Dual-Material Gate Junctionless Transistor With High- Spacer for Enhanced Analog Performance
RK Baruah, RP Paily
IEEE Transactions on electron devices 61 (1), 123-128, 2013
Pulsed laser deposition of TiO2 for MOS gate dielectric
R Paily, A DasGupta, N DasGupta, P Bhattacharya, P Misra, T Ganguli, ...
Applied Surface Science 187 (3-4), 297-304, 2002
Impact of high-k spacer on device performance of a junctionless transistor
RK Baruah, RP Paily
Journal of Computational Electronics 12, 14-19, 2013
High-throughput turbo decoder with parallel architecture for LTE wireless communication standards
R Shrestha, RP Paily
IEEE Transactions on Circuits and Systems I: Regular Papers 61 (9), 2699-2710, 2014
Efficient solar power management system for self-powered IoT node
S Mondal, R Paily
IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2359-2369, 2017
On-chip photovoltaic power harvesting system with low-overhead adaptive MPPT for IoT nodes
S Mondal, R Paily
IEEE Internet of Things Journal 4 (5), 1624-1633, 2017
High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule
S Kumawat, R Shrestha, N Daga, R Paily
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (5), 1421-1430, 2015
Single bit‐line 11T SRAM cell for low power and improved stability
R Lorenzo, R Pailly
IET Computers & Digital Techniques 14 (3), 114-121, 2020
Design and analysis of spiral inductors
G Haobijam, RP Palathinkal
Springer India, 2014
An improved ROM architecture for bubble error suppression in high speed flash ADCs
N Agrawal, R Paily
2008 Annual IEEE Student Paper Conference, 1-5, 2008
Blind navigation assistance for visually impaired based on local depth hypothesis from a single image
RG Praveen, RP Paily
Procedia Engineering 64, 351-360, 2013
An efficient on-chip switched-capacitor-based power converter for a microscale energy transducer
S Mondal, R Paily
IEEE Transactions on Circuits and Systems II: Express Briefs 63 (3), 254-258, 2015
FPGA implementation of image enhancement algorithms
S Sowmya, R Paily
2011 International Conference on Communications and Signal Processing, 584-588, 2011
Analysis of graphene tunnel field-effect transistors for analog/RF applications
B Rawat, R Paily
IEEE Transactions on Electron Devices 62 (8), 2663-2669, 2015
Mass loading in coupled resonators consisting of SU-8 micropillars fabricated over SAW devices
N Ramakrishnan, HB Nemade, RP Palathinkal
IEEE Sensors Journal 11 (2), 430-431, 2010
An area-throughput efficient FPGA implementation of the block cipher AES algorithm
B Jyrwa, R Paily
2009 International Conference on Advances in Computing, Control, and …, 2009
Two-Dimensional MoS2-Based Electrochemical Biosensor for Highly Selective Detection of Glutathione
B Rawat, KK Mishra, U Barman, L Arora, D Pal, RP Paily
IEEE Sensors Journal 20 (13), 6937-6944, 2020
A new PVT compensation technique based on current comparison for low-voltage, near sub-threshold LNA
MM Vinaya, R Paily, A Mahanta
IEEE transactions on circuits and systems I: regular papers 62 (12), 2908-2919, 2015
Resonant frequency characteristics of a SAW device attached to resonating micropillars
N Ramakrishnan, HB Nemade, RP Palathinkal
Sensors 12 (4), 3789-3797, 2012
Transition metal dichalcogenide-based field-effect transistors for analog/mixed-signal applications
B Rawat, MM Vinaya, R Paily
IEEE Transactions on Electron Devices 66 (5), 2424-2430, 2019
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