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Benjamin Hershberg
Benjamin Hershberg
Intel
Overená e-mailová adresa na: hershberg.com - Domovská stránka
Názov
Citované v
Citované v
Rok
Ring amplifiers for switched capacitor circuits
B Hershberg, S Weaver, K Sobue, S Takeuchi, K Hamashita, UK Moon
IEEE Journal of Solid-State Circuits 47 (12), 2928-2942, 2012
2362012
Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells.
S Weaver, BP Hershberg, UK Moon
IEEE Trans. on circuits and systems 61 (1), 84-91, 2014
1992014
A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28nm CMOS with 280fs RMS jitter
K Raczkowski, N Markulic, B Hershberg, J Van Driessche, J Craninckx
Radio Frequency Integrated Circuits Symposium, 2014 IEEE, 89-92, 2014
1512014
A+ 70-dBm IIP3 Electrical-Balance Duplexer for Highly Integrated Tunable Front-Ends
B van Liempd, B Hershberg, S Ariumi, K Raczkowski, KF Bink, U Karthaus, ...
IEEE Transactions on Microwave Theory and Techniques 64 (12), 4274-4286, 2016
1212016
Stochastic flash analog-to-digital conversion
S Weaver, B Hershberg, P Kurahashi, D Knierim, UK Moon
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (11), 2825-2833, 2010
1162010
A+ 70dBm IIP3 Single-Ended Electrical-Balance Duplexer in 0.18 μm SOI CMOS
B van Liempd, B Hershberg, K Raczkowski, S Ariumi, U Karthaus, KF Bink, ...
ISSCC Dig. Tech. Papers, 32-33, 2015
93*2015
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS
J Lagos, B Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits, 2018
792018
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers
J Lagos, BP Hershberg, E Martens, P Wambacq, J Craninckx
IEEE Journal of Solid-State Circuits 54 (3), 646-658, 2019
752019
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation
N Markulic, K Raczkowski, E Martens, PE Paro Filho, B Hershberg, ...
IEEE Journal of Solid-State Circuits 51 (12), 3078-3092, 2016
682016
Design of a split-CLS pipelined ADC with full signal swing using an accurate but fractional signal swing opamp
B Hershberg, S Weaver, UK Moon
IEEE Journal of Solid-State Circuits 45 (12), 2623-2633, 2010
582010
A 75.9 dB-SNDR 2.96 mW 29fJ/conv-step ringamp-only pipelined ADC
B Hershberg, UK Moon
2013 Symposium on VLSI Circuits, C94-C95, 2013
462013
A 3.2 GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion
B Hershberg, D Dermit, B van Liempd, E Martens, N Markulic, J Lagos, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 58-60, 2019
432019
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization
E Martens, B Hershberg, J Craninckx
IEEE Journal of Solid-State Circuits 53 (4), 1161-1171, 2018
432018
A 6b stochastic flash analog-to-digital converter without calibration or reference ladder
S Weaver, B Hershberg, D Knierim, UK Moon
2008 IEEE Asian Solid-State Circuits Conference, 373-376, 2008
392008
Real-Time RF Self-Interference Cancellation for In-Band Full Duplex
T Vermeulen, B van Liempd, B Hershberg, S Pollin
352015
A 61.5 dB SNDR pipelined ADC using simple highly-scalable ring amplifiers
B Hershberg, S Weaver, K Sobue, S Takeuchi, K Hamashita, UK Moon
2012 Symposium on VLSI Circuits (VLSIC), 32-33, 2012
352012
An electrical-balance duplexer for in-band full-duplex with<-85dBm in-band distortion at+ 10dBm TX-power
B van Liempd, B Hershberg, B Debaillie, P Wambacq, J Craninckx
European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2015-41st, 176-179, 2015
342015
A 10.0 ENOB, 6.2 fJ/conv.-step, 500 MS/s Ringamp-Based Pipelined-SAR ADC with Background Calibration and Dynamic Reference Regulation in 16nm CMOS
J Lagos, N Markulic, B Hershberg, D Dermit, M Shrivas, E Martens, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
322021
In-band full-duplex transceiver technology for 5G mobile networks
B Debaillie, B van Liempd, B Hershberg, J Craninckx, K Rikkinen, ...
ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015
302015
A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers
B Hershberg, B van Liempd, X Zhang, P Wambacq, J Craninckx
2016 IEEE International Solid-State Circuits Conference (ISSCC), 356-357, 2016
292016
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