Hans-Joachim Wunderlich
Hans-Joachim Wunderlich
Professor Emeritus of Computer Science, University of Stuttgart
Verified email at - Homepage
Cited by
Cited by
Minimized Power Consumption for Scan-Based BIST
S Gerstendörfer, HJ Wunderlich
IEEE International Test Conference (ITC'99) 30, 77-84, 1999
Bit-flipping BIST
HJ Wunderlich, G Kiefer
Proceedings of International Conference on Computer Aided Design, 337-343, 1996
Multiple distributions for biased random test patterns
HJ Wunderlich
IEEE transactions on computer-aided design of integrated circuits and …, 1990
Power-aware design-for-test
HJ Wunderlich, CG Zoellin
Power-Aware Testing and Test Strategies for Low Power Devices, 117-146, 2010
A modified clock scheme for a low power BIST test pattern generator
P Girard, L Guiller, C Landrault, S Pravossoudovitch, HJ Wunderlich
Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, 306-311, 2001
Pattern generation for a deterministic BIST scheme
S Hellebrand, B Reeb, S Tarnick, HJ Wunderlich
Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995
A mixed mode BIST scheme based on reseeding of folding counters
S Hellebrand, HG Liang, HJ Wunderlich
Journal of Electronic Testing 17, 341-349, 2001
Low power serial built-in self-test
A Hertwig, HJ Wunderlich
Proceedings of IEEE European Test Workshop, 1998, 1998
Two-dimensional test data compression for scan-based deterministic BIST
HG Liang, S Hellebrand, HJ Wunderlich
Journal of Electronic Testing 18, 159-170, 2002
Adaptive Debug and Diagnosis Without Fault Dictionaries
S Holst, HJ Wunderlich
IEEE European Test Symposium (ETS'07) 12, 7-12, 2007
PROTEST: A tool for probabilistic testability analysis
HJ Wunderlich
22nd ACM/IEEE Design Automation Conference, 204-211, 1985
An analytical approach to the partial scan problem
A Kunzmann, HJ Wunderlich
Journal of Electronic Testing 1, 163-174, 1990
X-Masking During Logic BIST and its Impact on Defect Coverage
Y Tang, HJ Wunderlich, P Engelke, I Polian, B Becker, J Schlöffel, ...
IEEE Transactions on Very Large Scale Integrated (VLSI) Systems 14 (2), 193-202, 2006
Self test using unequiprobable random patterns
HJ Wunderlich
Verlag nicht ermittelbar, 1987
Application of deterministic logic BIST on industrial circuits
G Kiefer, H Vranken, E Jan Marinissen, HJ Wunderlich
Journal of Electronic Testing 17, 351-362, 2001
An integrated built-in test and repair approach for memories with 2D redundancy
P Ohler, S Hellebrand, HJ Wunderlich
12th IEEE European Test Symposium (ETS'07), 91-96, 2007
Design and architectures for dependable embedded systems
J Henkel, L Bauer, J Becker, O Bringmann, U Brinkschulte, S Chakraborty, ...
Proceedings of the seventh IEEE/ACM/IFIP international conference on …, 2011
Zuverlässigkeit mechatronischer Systeme: Grundlagen und Bewertung in frühen Entwicklungsphasen
B Bertsche, P Göhner, U Jensen, W Schinköthe, HJ Wunderlich
Springer-Verlag, 2009
Mixed-Mode BIST Using Embedded Processors
S Hellebrand, HJ Wunderlich, A Hertwig
IEEE International Test Conference (ITC'96) 27, 195-204, 1996
Accumulator based deterministic BIST
R Dorsch, HJ Wunderlich
Proceedings International Test Conference 1998 (IEEE Cat. No. 98CH36270 …, 1998
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