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Hiroaki Shikano
Hiroaki Shikano
Overená e-mailová adresa na: hitachi.com
Názov
Citované v
Citované v
Rok
Method for controlling heterogeneous multiprocessor and multigrain parallelizing compiler
H Kasahara, K Kimura, J Shirako, Y Wada, M Ito, H Shikano
US Patent 8,250,548, 2012
1202012
A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications
T Enomoto, Y Oka, H Shikano
IEEE journal of solid-state circuits 38 (7), 1220-1226, 2003
982003
Multiprocessor system and multigrain parallelizing compiler
H Kasahara, K Kimura, J Shirako, M Ito, H Shikano
US Patent 7,895,453, 2011
722011
Global compiler for controlling heterogeneous multiprocessor
H Kasahara, K Kimura, H Shikano
US Patent 8,051,412, 2011
692011
Operating plan formulation support system and method
H Shikano
US Patent App. 14/299,575, 2014
672014
Multi-sensing devices cooperative recognition system
H Shikano, N Irie
US Patent 7,340,078, 2008
622008
Compiler control power saving scheme for multi core processors
J Shirako, N Oshiyama, Y Wada, H Shikano, K Kimura, H Kasahara
International Workshop on Languages and Compilers for Parallel Computing …, 2005
522005
A self-controllable-voltage-level (SVL) circuit for low-power, high-speed CMOS circuits
T Enomoto, Y Oka, H Shikano, T Harada
Proceedings of the 28th European Solid-State Circuits Conference, 411-414, 2002
422002
Controlling body-bias voltage and clock frequency in a multiprocessor system for processing tasks
H Shikano
US Patent 8,112,754, 2012
382012
Information processing device, information processing system, and information processing method
H Shikano
US Patent App. 13/577,555, 2012
332012
Heterogeneous multi-core architecture that enables 54x AAC-LC stereo encoding
H Shikano, M Ito, M Onouchi, T Todaka, T Tsunoda, T Kodama, ...
IEEE Journal of Solid-State Circuits 43 (4), 902-910, 2008
272008
in-facility information provision system and in-facility information provision method
H Shikano, N Irie, A Ito, J Inaba, M Inoue, K Sakai
US Patent 7,454,216, 2008
242008
Node processing device and its processing method
H Shikano, Y Ogata
US Patent 8,635,263, 2014
192014
Multiprocessor system
H Shikano, N Irie
US Patent App. 11/203,284, 2006
192006
Heterogeneous multicore processor technologies for embedded systems
K Uchiyama, F Arakawa, H Kasahara, T Nojiri, H Noda, Y Tawara, ...
Springer New York, 2012
162012
Performance evaluation of heterogeneous chip multi-processor with MP3 audio encoder
H Shikano, Y Suzuki, Y Wada, J Shirako, K Kimura, H Kasahara
IEEE Symposium on Low-Power and High Speed Chips (COOL Chips IX), 349-363, 2006
142006
Multiprocessor system and multigrain parallelizing compiler
H Kasahara, K Kimura, J Shirako, M Ito, H Shikano
US Patent 8,812,880, 2014
132014
Operation managing device and operation management method
H Shikano, J Yamamoto, T Saito
US Patent 8,990,372, 2015
112015
Cloud architecture for tight interaction with the real world and deep sensor-data aggregation mechanism
H Aoki, H Shikano, M Okuno, Y Ogata, H Miyamoto, Y Tsushima, T Yazaki, ...
SoftCOM 2010, 18th International Conference on Software, Telecommunications …, 2010
112010
マルチコアプロセッサにおけるコンパイラ制御低消費電力化手法
白子準, 吉田宗弘, 押山直人, 和田康孝, 中野浩史, 鹿野裕明, 木村啓二, ...
情報処理学会論文誌コンピューティングシステム (ACS) 47 (SIG12 (ACS15)), 147-158, 2006
112006
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