| The CHERI capability model: Revisiting RISC in an age of risk J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ... 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014 | 209 | 2014 |
| Cheri: A hybrid capability-system architecture for scalable software compartmentalization RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ... 2015 IEEE Symposium on Security and Privacy, 20-37, 2015 | 166 | 2015 |
| ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS A Armstrong, C Pulte, S Flur, I Stark, N Krishnaswami, P Sewell, ... | 39 | 2019 |
| Capability hardware enhanced risc instructions: Cheri instruction-set architecture (version 5) RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ... University of Cambridge, Computer Laboratory, 2016 | 38 | 2016 |
| Fast protection-domain crossing in the cheri capability-system architecture RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ... IEEE Micro 36 (5), 38-49, 2016 | 28 | 2016 |
| CHERI JNI: Sinking the Java security model into the C D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ... ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017 | 21 | 2017 |
| CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ... Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 20 | 2019 |
| Capability hardware enhanced RISC instructions: CHERI instruction-set architecture RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ... University of Cambridge, Computer Laboratory, 2015 | 19 | 2015 |
| Cheri concentrate: Practical compressed capabilities J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ... IEEE Transactions on Computers 68 (10), 1455-1469, 2019 | 17 | 2019 |
| Bluespec Extensible RISC Implementation: BERI Hardware reference RNM Watson, J Woodruff, D Chisnall, B Davis, W Koszek, AT Markettos, ... University of Cambridge, Computer Laboratory, 2015 | 12 | 2015 |
| Rigorous engineering for hardware security: formal modelling and proof in the CHERI design and implementation process K Nienhuis, A Joannou, A Fox, M Roe, T Bauereiss, B Campbell, M Naylor, ... University of Cambridge, Computer Laboratory, 2019 | 9 | 2019 |
| Cornucopia: Temporal Safety for CHERI Heaps NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ... 2020 IEEE Symposium on Security and Privacy (SP). Los Alamitos, CA, USA …, 2020 | 6 | 2020 |
| Department of Computer Science and Technology L Wang, G Tyson, J Kangasharju, J Crowcroft, S Bayhan, J Ott, ... IEEE Transactions on Big Data, 2016 | 6 | 2016 |
| Detailed models of instruction set architectures: From pseudocode to formal semantics A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ... Proceedings of the 25th Automated Reasoning Workshop, 13, 2018 | 5 | 2018 |
| Hardware support for compartmentalisation RM Norton University of Cambridge, Computer Laboratory, 2016 | 3 | 2016 |
| Modular Research-Based Composably Trustworthy Mission-Oriented Resilient Clouds (MRC2) PG Neumann, SW Moore, RN Watson, J Anderson, N Dave, B Davis, ... SRI INTERNATIONAL Menlo Park United States, 2016 | 2 | 2016 |
| How FreeBSD Boots: a soft-core MIPS perspective B Davis, R Norton, J Woodruff, RNM Watson Proceedings of AsiaBSDCon, 2014 | 2 | 2014 |
| Research data supporting'Cornucopia: Temporal Safety for CHERI Heaps' N Filardo, B Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, H Xia, ... | | 2020 |
| The CHERI capability model J Anderson, BL Brooks Davis, PG Neumann, R Norton, M Roe | | |
