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Robert Norton
Robert Norton
Verified email at cl.cam.ac.uk
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Cited by
Year
The CHERI capability model: Revisiting RISC in an age of risk
J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ...
2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA …, 2014
2992014
CHERI: A hybrid capability-system architecture for scalable software compartmentalization
RNM Watson, J Woodruff, PG Neumann, SW Moore, J Anderson, ...
2015 IEEE Symposium on Security and Privacy, 20-37, 2015
2402015
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS
A Armstrong, T Bauereiss, B Campbell, A Reid, KE Gray, R Norton-Wright, ...
Association for Computing Machinery (ACM), 2019
922019
Capability hardware enhanced risc instructions: Cheri instruction-set architecture (version 5)
RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ...
University of Cambridge, Computer Laboratory, 2016
712016
CheriABI: Enforcing valid pointer provenance and minimizing pointer privilege in the POSIX C run-time environment
B Davis, RNM Watson, A Richardson, PG Neumann, SW Moore, ...
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
512019
Cheri concentrate: Practical compressed capabilities
J Woodruff, A Joannou, H Xia, A Fox, RM Norton, D Chisnall, B Davis, ...
IEEE Transactions on Computers 68 (10), 1455-1469, 2019
462019
Fast protection-domain crossing in the CHERI capability-system architecture
RNM Watson, RM Norton, J Woodruff, SW Moore, PG Neumann, ...
IEEE Micro 36 (5), 38-49, 2016
452016
CHERI JNI: Sinking the Java security model into the C
D Chisnall, B Davis, K Gudka, D Brazdil, A Joannou, J Woodruff, ...
ACM SIGARCH Computer Architecture News 45 (1), 569-583, 2017
422017
Cornucopia: Temporal safety for CHERI heaps
NW Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, B Davis, ...
2020 IEEE Symposium on Security and Privacy (SP), 608-625, 2020
342020
Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process
K Nienhuis, A Joannou, T Bauereiss, A Fox, M Roe, B Campbell, M Naylor, ...
2020 IEEE Symposium on Security and Privacy (SP), 1003-1020, 2020
322020
Capability hardware enhanced RISC instructions: CHERI instruction-set architecture
RNM Watson, PG Neumann, J Woodruff, M Roe, J Anderson, D Chisnall, ...
University of Cambridge, Computer Laboratory, 2015
262015
The CHERI capability model: Revisiting RISC in an age of risk. In 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)
J Woodruff, RNM Watson, D Chisnall, SW Moore, J Anderson, B Davis, ...
IEEE, 2014
232014
Bluespec Extensible RISC Implementation: BERI Hardware reference
RNM Watson, J Woodruff, D Chisnall, B Davis, W Koszek, AT Markettos, ...
University of Cambridge, Computer Laboratory, 2015
142015
Detailed models of instruction set architectures: From pseudocode to formal semantics
A Armstrong, T Bauereiss, B Campbell, S Flur, KE Gray, P Mundkur, ...
Proceedings of the 25th Automated Reasoning Workshop: Bridging the Gap …, 2018
102018
A probability model for overflow sufficiency in small hash tables
RM Norton, DP Yeager
Communications of the ACM 28 (10), 1068-1075, 1985
81985
Hardware support for compartmentalisation
RM Norton
University of Cambridge, Computer Laboratory, 2016
42016
Modular research-based composably trustworthy mission-oriented resilient clouds (mrc2)
PG Neumann, SW Moore, RN Watson, J Anderson, N Dave, B Davis, ...
SRI INTERNATIONAL Menlo Park United States, 2016
22016
How FreeBSD Boots: a soft-core MIPS perspective
B Davis, R Norton, J Woodruff, RNM Watson
Proceedings of AsiaBSDCon, 2014
22014
Cornucopia: Temporal safety for CHERI heaps
N Wesley Filardo, BF Gutstein, J Woodruff, S Ainsworth, L Paul-Trifu, ...
IEEE, 2020
12020
Department of Computer Science and Technology
L Wang, G Tyson, J Kangasharju, J Crowcroft, S Bayhan, J Ott, ...
IEEE Transactions on Big Data, 2016
12016
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