| Functionality matters in netlist representation learning Z Wang, C Bai, Z He, G Zhang, Q Xu, TY Ho, B Yu, Y Huang Proceedings of the 59th ACM/IEEE Design Automation Conference, 61-66, 2022 | 45 | 2022 |
| The dawn of ai-native eda: Promises and challenges of large circuit models L Chen, Y Chen, Z Chu, W Fang, TY Ho, Y Huang, S Khan, M Li, X Li, ... arXiv e-prints, arXiv: 2403.07257, 2024 | 35* | 2024 |
| Graph learning-based arithmetic block identification Z He*, Z Wang*, C Bai, H Yang, B Yu 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2021 | 34 | 2021 |
| Restructure-tolerant timing prediction via multimodal fusion Z Wang, S Liu, Y Pu, S Chen, TY Ho, B Yu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 21* | 2023 |
| Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement S Liu*, Z Wang*, F Liu, Y Lin, B Yu, M Wong 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 8 | 2023 |
| Efficient arithmetic block identification with graph learning and network-flow Z Wang, Z He, C Bai, H Yang, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 7 | 2022 |
| Fgnn2: A powerful pre-training framework for learning the logic functionality of circuits Z Wang, C Bai, Z He, G Zhang, Q Xu, TY Ho, Y Huang, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 4 | 2024 |
| Routing-aware legal hybrid bonding terminal assignment for 3D face-to-face stacked ics S Liu, J Jiang, Z He, Z Wang, Y Lin, B Yu, M Wong Proceedings of the 2024 International Symposium on Physical Design, 75-82, 2024 | 3 | 2024 |
| Disentangle, align and generalize: Learning a timing predictor from different technology nodes X Zhang, B Zhu, F Liu, Z Wang, P Xu, H Xu, B Yu Proceedings of the 61st ACM/IEEE Design Automation Conference, 1-6, 2024 | 2 | 2024 |
| Parsgcn: Bridging the gap between emulation partitioning and scheduling Z Wang, W Zhao, Y Pu, L Chen, WWK Thong, W Sheng, TY Ho, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 1 | 2024 |
| HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning Y Pu, F Liu, Z He, K Zhu, R Fu, Z Wang, TY Ho, B Yu International Symposium on Physical Design (ISPD’25), 2025 | | 2025 |
| Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits S Lee, Z Wang, S Kim, T Lee, DZ Pan arXiv preprint arXiv:2502.08949, 2025 | | 2025 |
| GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays F Liu, G Guo, Y Ye, Z Wang, W Fu, W Sheng, B Yu | | 2025 |
| Pre-Routing Timing Prediction Across Different Technology Nodes X Zhang, B Zhu, F Liu, J Jiang, Z Wang, P Xu, H Xu, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
| Sign-Off Timing Considerations via Concurrent Routing Topology Optimization S Liu*, Z Wang*, F Liu, Y Lin, B Yu, M Wong IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | | 2024 |
Bei YuThe Chinese University of Hong KongVerified email at cse.cuhk.edu.hk
