An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With W/Channel in 65-nm CMOS AT Do, SMA Zeinolabedin, D Jeon, D Sylvester, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27 (1), 126-137, 2018 | 37 | 2018 |
A 128-Channel Spike Sorting Processor Featuring 0.175 µW and 0.0033 mm2 per Channel in 65-nm CMOS SMA Zeinolabedin, AT Do, D Jeon, D Sylvester, TH Kim Symposium on VLSI Circuits, 2016 | 26 | 2016 |
A 16-Channel Fully Configurable Neural SoC With 1.52 W/Ch Signal Acquisition, 2.79 W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural … SMA Zeinolabedin, FM Schüffny, R George, F Kelber, H Bauer, S Scholze, ... IEEE Transactions on Biomedical Circuits and Systems 16 (1), 94-107, 2022 | 21 | 2022 |
Energy-efficient data-aware SRAM design utilizing column-based data encoding AT Do, SMA Zeinolabedin, TTH Kim IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 2154-2158, 2019 | 10 | 2019 |
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits SMA Zeinolabedin, AT Do, KS Yeo, TTH Kim 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 794-797, 2015 | 10 | 2015 |
An area-and energy-efficient FIFO design using error-reduced data compression and near-threshold operation for image/video applications SMA Zeinolabedin, J Zhou, X Liu, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (11 …, 2014 | 10 | 2014 |
Real-time hardware implementation of arm coresight trace decoder SMA Zeinolabedin, J Partzsch, C Mayr IEEE Design & Test 38 (1), 69-77, 2020 | 9 | 2020 |
Low computational complexity hardware implementation of Laplacian Pyramid SMA Zeinolabedin, N Karimi, S Samavi 2010 18th Iranian Conference on Electrical Engineering, 465-470, 2010 | 8 | 2010 |
An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology F Schüffny, S Höppner, S Hänzsche, RM George, SMA Zeinolabedin, ... IEEE Transactions on Circuits and Systems II: Express Briefs, 2021 | 7 | 2021 |
Analyzing ARM CoreSight ETMV4.X Data Trace Stream with a Real-Time Hardware Accelerator SMA Zeinolabedin, J Partzsch, C Mayr Design, Automation and Test in Europe Conference, 2021 | 5 | 2021 |
Contourlet based image compression using controlled modification of coefficients N Karimi, S Samavi, S Shirani, H Talebi, SMA Zaynolabedin 2009 Canadian Conference on Electrical and Computer Engineering, 991-994, 2009 | 5 | 2009 |
A 0.3 PJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications AT Do, SMA Zeinolabedin, TT Kim 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), 173-176, 2016 | 4 | 2016 |
A 64-channel back-gate adapted ultra-low-voltage spike-aware neural recording front-end with on-chip lossless/near-lossless compression engine and 3.3 v stimulator in 22nm fdsoi FM Schüffny, SMA Zeinolabedin, R George, L Guo, A Weiße, J Uhlig, ... 2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2022 | 3 | 2022 |
An area-and power-efficient FIFO with error-reduced data compression for image/video processing SMA Zeinolabedin, J Zhou, X Liu, TT Kim 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2277-2280, 2014 | 3 | 2014 |
A new quantization algorithm for fir filters coefficients SMA Zeinolabedin, N Karimi 20th Iranian Conference on Electrical Engineering (ICEE2012), 1120-1124, 2012 | 3 | 2012 |
A Power and Area Efficient Ultra-low Voltage Laplacian Pyramid Processing Engine with Adaptive Data Compression SMA Zeinolabedin, J Zhou, X Liu, TH Kim IEEE Transactions on Circuits and Systems-I (TCAS-I), 2016 | 2 | 2016 |
A 0.5 V power and area efficient laplacian pyramid processing engine using FIFO with adaptive data compression SMA Zeinolabedin, J Zhou, X Liu, TT Kim ESSCIRC Conference 2015-41st European Solid-State Circuits Conference …, 2015 | 2 | 2015 |
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI L Guo, M Jobst, J Partzsch, S Scholze, A Dixius, M Lohrmann, ... 2023 IEEE 5th International Conference on Artificial Intelligence Circuits …, 2023 | 1 | 2023 |
Various distance metrics evaluation on neural spike classification S Guo, L Guo, SMA Zeinolabedin, C Mayr 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), 554-558, 2022 | 1 | 2022 |
How to design an input stage for neural recording system in 22 nm FDSOI FM Schuffny, S Höppner, SMA Zeinolabedin, RM George, C Mayr 2022 17th Conference on Ph. D Research in Microelectronics and Electronics …, 2022 | 1 | 2022 |