| Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform Y Xin, B Liu, B Min, WXY Li, RCC Cheung, AS Fong, TF Chan Microelectronics Journal 44 (8), 670-682, 2013 | 22 | 2013 |
| GPU-based biclustering for microarray data analysis in neurocomputing B Liu, Y Xin, RCC Cheung, H Yan Neurocomputing 134, 239-246, 2014 | 16 | 2014 |
| HybridTSS: A recursive scheme combining coarse-and fine-grained tuples for packet classification Y Liu, Y Xin, W Li, H Song, O Rottenstreich, G Xie, W Li, Y Wang Proceedings of the 6th Asia-Pacific Workshop on Networking, 43-49, 2022 | 9 | 2022 |
| FPGA-based updatable packet classification using TSS-combined bit-selecting tree Y Xin, W Li, G Tang, T Yang, X Hu, Y Wang IEEE/ACM Transactions on Networking 30 (6), 2760-2775, 2022 | 9 | 2022 |
| FPga-Based high-Performance collision Detection: an enabling Technique for image-guided robotic surgery Z Zhang, Y Xin, B Liu, WXY Li, KH Lee, CF Ng, D Stoyanov, RCC Cheung, ... Frontiers in Robotics and AI 3, 51, 2016 | 9 | 2016 |
| An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking Y Xin, WXY Li, RCC Cheung, RHM Chan, H Yan, D Song, TW Berger Microelectronics Journal 45 (6), 690-701, 2014 | 9 | 2014 |
| KickTree: A recursive algorithmic scheme for packet classification with bounded worst-case performance Y Xin, Y Liu, W Li, R Yao, Y Xu, Y Wang Proceedings of the Symposium on Architectures for Networking and …, 2021 | 6 | 2021 |
| Laguerre-Volterra model and architecture for MIMO system identification and output prediction WXY Li, Y Xin, RHM Chan, D Song, TW Berger, RCC Cheung 2014 36th Annual International Conference of the IEEE Engineering in …, 2014 | 6 | 2014 |
| A parallel and updatable architecture for FPGA-based packet classification with large-scale rule sets Y Xin, W Li, G Xie, Y Xu, Y Wang IEEE Micro 43 (2), 110-119, 2023 | 5 | 2023 |
| An application specific instruction set processor (asip) for adaptive filters in neural prosthetics Y Xin, WXY Li, Z Zhang, RCC Cheung, D Song, TW Berger IEEE/ACM Transactions on Computational Biology and Bioinformatics 12 (5 …, 2015 | 5 | 2015 |
| High throughput hardware/software heterogeneous system for RRPN-based scene text detection Y Xin, D Chen, C Zeng, W Zhang, Y Wang, RCC Cheung IEEE Transactions on Computers 71 (7), 1507-1521, 2021 | 4 | 2021 |
| Adderic: towards low computation cost image compression B Li, Y Xin, C Li, Y Bao, F Meng, Y Liang ICASSP 2022-2022 IEEE International Conference on Acoustics, Speech and …, 2022 | 3 | 2022 |
| An fpga-based high-throughput packet classification architecture supporting dynamic updates for large-scale rule sets Y Xin, W Li, Y Wang, S Yao IEEE INFOCOM 2021-IEEE Conference on Computer Communications Workshops …, 2021 | 3 | 2021 |
| An FPGA-based high-performance neural ensemble spiking activity simulator utilizing generalized Volterra kernel and complexity analysis WXY Li, RCC Cheung, Y Xin, D Song, TW Berger Journal of Circuits, Systems and Computers 25 (01), 1640004, 2016 | 3 | 2016 |
| A novel low-latency scheduling approach of TSN for multi-link rate networking X Zheng, Y Liu, S Zhan, Y Xin, Y Wang Computer Networks 240, 110184, 2024 | 2 | 2024 |
| Updatable Packet Classification on FPGA with Bounded Worst-Case Performance Y Xin, W Li, G Xie, Y Xu, Y Wang HOT Interconnets 2022, 2022 | 2 | 2022 |
| Recursive Multi-Tree Construction With Efficient Rule Sifting for Packet Classification on FPGA Y Xin, W Li, C Jia, X Li, Y Xu, B Liu, Z Tian, W Zhang IEEE/ACM Transactions on Networking, 2023 | 1 | 2023 |
| MCCQF: Low-Latency Transmission Based on IEEE 802.1 Qch For Hierarchical Networking Y Liu, D Zhou, S Zhan, Y Xin, J Lin, X Feng, E Shi, Y Qi, G Chen, J Zheng, ... ICC 2023-IEEE International Conference on Communications, 6052-6058, 2023 | 1 | 2023 |
| Bubble Sketch: A High-performance and Memory-efficient Sketch for Finding Top-k Items in Data Streams L Cao, Q Shi, Y Liu, H Zheng, Y Xin, W Li, T Yang, Y Wang, Y Xu, ... Proceedings of the 33rd ACM International Conference on Information and …, 2024 | | 2024 |
| A Heterogeneous and Adaptive Architecture for Decision-tree-based ACL Engine on FPGA Y Xin, C Jia, W Li, O Rottenstreich, Y Xu, G Xie, Z Tian, J Li IEEE Transactions on Computers, 2024 | | 2024 |
