| Face recognition using transform domain feature extraction and PSO-based feature selection NLA Krisshna, VK Deepak, K Manikantan, S Ramachandran Applied Soft Computing 22, 141-161, 2014 | 120 | 2014 |
| Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip PY Chen, D Kadetotad, Z Xu, A Mohanty, B Lin, J Ye, S Vrudhula, J Seo, ... 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 854-859, 2015 | 102 | 2015 |
| A 1.06- W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring S Yin, M Kim, D Kadetotad, Y Liu, C Bae, SJ Kim, Y Cao, J Seo IEEE Journal of Solid-State Circuits 54 (8), 2316-2326, 2019 | 85 | 2019 |
| Parallel architecture with resistive crosspoint array for dictionary learning acceleration D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ... IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 77 | 2015 |
| An 8.93 TOPS/W LSTM recurrent neural network accelerator featuring hierarchical coarse-grain sparsity for on-device speech recognition D Kadetotad, S Yin, V Berisha, C Chakrabarti, J Seo IEEE Journal of Solid-State Circuits 55 (7), 1877-1887, 2020 | 62 | 2020 |
| Efficient memory compression in deep neural networks using coarse-grain sparsification for speech applications D Kadetotad, S Arunachalam, C Chakrabarti, J Seo 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 49 | 2016 |
| ECG authentication hardware design with low-power signal processing and neural network optimization with low precision and structured compression SK Cherupally, S Yin, D Kadetotad, G Srivastava, C Bae, SJ Kim, J Seo IEEE transactions on biomedical circuits and systems 14 (2), 198-208, 2020 | 40* | 2020 |
| Memory compression in a deep neural network J Seo, D Kadetotad, S Arunachalam, C Chakrabarti US Patent 10,614,798, 2020 | 29 | 2020 |
| On-chip sparse learning acceleration with CMOS and resistive synaptic devices J Seo, B Lin, M Kim, PY Chen, D Kadetotad, Z Xu, A Mohanty, S Vrudhula, ... IEEE Transactions on Nanotechnology 14 (6), 969-979, 2015 | 29 | 2015 |
| A 8.93-TOPS/W LSTM recurrent neural network accelerator featuring hierarchical coarse-grain sparsity with all parameters stored on-chip D Kadetotad, V Berisha, C Chakrabarti, JS Seo ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 23 | 2019 |
| Neuromorphic hardware accelerator for SNN inference based on STT-RAM crossbar arrays SR Kulkarni, DV Kadetotad, S Yin, JS Seo, B Rajendran 2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019 | 21 | 2019 |
| Parallel programming of resistive cross-point array for synaptic plasticity Z Xu, A Mohanty, PY Chen, D Kadetotad, B Lin, J Ye, S Vrudhula, S Yu, ... Procedia Computer Science 41, 126-133, 2014 | 21 | 2014 |
| A smart hardware security engine combining entropy sources of ECG, HRV, and SRAM PUF for authentication and secret key generation SK Cherupally, S Yin, D Kadetotad, C Bae, SJ Kim, J Seo IEEE Journal of Solid-State Circuits 55 (10), 2680-2690, 2020 | 19 | 2020 |
| Joint optimization of quantization and structured sparsity for compressed deep neural networks G Srivastava, D Kadetotad, S Yin, V Berisha, C Chakrabarti, J Seo ICASSP 2019-2019 IEEE International Conference on Acoustics, Speech and …, 2019 | 19 | 2019 |
| Neurophysics-inspired parallel architecture with resistive crosspoint array for dictionary learning D Kadetotad, Z Xu, A Mohanty, PY Chen, B Lin, J Ye, S Vrudhula, S Yu, ... 2014 IEEE Biomedical Circuits and Systems Conference (BioCAS) Proceedings …, 2014 | 14 | 2014 |
| Monolithic 3D IC designs for low-power deep neural networks targeting speech recognition K Chang, D Kadetotad, Y Cao, J Seo, SK Lim 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 13 | 2017 |
| Low-power neuromorphic speech recognition engine with coarse-grain sparsity S Yin, D Kadetotad, B Yan, C Song, Y Chen, C Chakrabarti, J Seo 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 111-114, 2017 | 13 | 2017 |
| Comprehensive evaluation of OpenCL-based CNN implementations for FPGAs R Tapiador-Morales, A Rios-Navarro, A Linares-Barranco, M Kim, ... Advances in Computational Intelligence: 14th International Work-Conference …, 2017 | 10* | 2017 |
| A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65 nm CMOS M Kim, A Mohanty, D Kadetotad, L Wei, X He, Y Cao, JS Seo IEEE Transactions on Circuits and Systems I: Regular Papers 66 (10), 3843-3853, 2019 | 9 | 2019 |
| Power, performance, and area benefit of monolithic 3D ICs for on-chip deep neural networks targeting speech recognition K Chang, D Kadetotad, Y Cao, JS Seo, SK Lim ACM Journal on Emerging Technologies in Computing Systems (JETC) 14 (4), 1-19, 2018 | 8 | 2018 |
Jae-sun SeoCornell TechVerified email at cornell.edu
