| ASAP7: A 7-nm finFET predictive process design kit LT Clark, V Vashishtha, L Shifren, A Gujja, S Sinha, B Cline, ... Microelectronics Journal 53, 105-115, 2016 | 553 | 2016 |
| Exploring sub-20nm FinFET design with predictive technology models S Sinha, G Yeric, V Chandra, B Cline, Y Cao Proceedings of the 49th Annual Design Automation Conference, 283-288, 2012 | 378 | 2012 |
| Exploring variability and performance in a sub-200-mV processor S Hanson, B Zhai, M Seok, B Cline, K Zhou, M Singhal, M Minuth, J Olson, ... IEEE Journal of Solid-State Circuits 43 (4), 881-891, 2008 | 198 | 2008 |
| Analysis and modeling of CD variation for statistical static timing B Cline, K Chopra, D Blaauw, Y Cao Proceedings of the 2006 IEEE/ACM international conference on Computer-aided …, 2006 | 106 | 2006 |
| Performance and variability optimization strategies in a sub-200mV, 3.5 pJ/inst, 11nW subthreshold processor S Hanson, B Zhai, M Seok, B Cline, K Zhou, M Singhal, M Minuth, J Olson, ... 2007 IEEE Symposium on VLSI Circuits, 152-153, 2007 | 100 | 2007 |
| Correlated electron switch programmable fabric L Shifren, G Yeric, S Sinha, B Cline, V Chandra US Patent 10,056,143, 2018 | 93 | 2018 |
| Self-aligned double patterning aware pin access and standard cell layout co-optimization X Xu, B Cline, G Yeric, B Yu, DZ Pan Proceedings of the 2014 on International symposium on physical design, 101-108, 2014 | 88 | 2014 |
| Computer implemented system and method for generating a layout of a cell defining a circuit component P De Dood, MW Frederick, JC Wang, BDN Lee, BT Cline, X Xu, AW Chen, ... US Patent 10,083,269, 2018 | 82 | 2018 |
| Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm D Prasad, SST Nibhanupudi, S Das, O Zografos, B Chehab, S Sarkar, ... 2019 IEEE International Electron Devices Meeting (IEDM), 19.1. 1-19.1. 4, 2019 | 72 | 2019 |
| Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools K Chang, S Sinha, B Cline, R Southerland, M Doherty, G Yeric, SK Lim 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2016 | 67 | 2016 |
| Standard cell library design and optimization methodology for ASAP7 PDK X Xu, N Shah, A Evans, S Sinha, B Cline, G Yeric 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 999 …, 2017 | 54 | 2017 |
| Replacing copper interconnects with graphene at a 7-nm node NC Wang, S Sinha, B Cline, CD English, G Yeric, E Pop 2017 IEEE International Interconnect Technology Conference (IITC), 1-3, 2017 | 45 | 2017 |
| Design benchmarking to 7nm with FinFET predictive technology models S Sinha, B Cline, G Yeric, V Chandra, Y Cao Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012 | 40 | 2012 |
| 32-bit processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance CS Lee, B Cline, S Sinha, G Yeric, HSP Wong 2016 IEEE international electron devices meeting (IEDM), 28.3. 1-28.3. 4, 2016 | 37 | 2016 |
| Physical design and FinFETs R Aitken, G Yeric, B Cline, S Sinha, L Shifren, I Iqbal, V Chandra Proceedings of the 2014 on International symposium on physical design, 65-68, 2014 | 37 | 2014 |
| Stress aware layout optimization V Joshi, B Cline, D Sylvester, D Blaauw, K Agarwal Proceedings of the 2008 international symposium on Physical design, 168-174, 2008 | 36 | 2008 |
| The past present and future of design-technology co-optimization G Yeric, B Cline, S Sinha, D Pietromonaco, V Chandra, R Aitken Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013 | 34 | 2013 |
| Circuit and method for configurable impedance array AJ Bhavnagarwala, V Chandra, BT Cline US Patent 9,773,550, 2017 | 32 | 2017 |
| Predictive simulation and benchmarking of Si and Ge pMOS FinFETs for future CMOS technology L Shifren, R Aitken, AR Brown, V Chandra, B Cheng, C Riddet, ... IEEE Transactions on Electron Devices 61 (7), 2271-2277, 2014 | 32 | 2014 |
| Leakage power reduction using stress-enhanced layouts V Joshi, B Cline, D Sylvester, D Blaauw, K Agarwal Proceedings of the 45th annual Design Automation Conference, 912-917, 2008 | 28 | 2008 |
Saurabh SinhaEngineer, AppleVerified email at apple.com
