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John Zedlewski
John Zedlewski
Verified email at nvidia.com
Title
Cited by
Cited by
Year
Modeling {Hard-Disk} power consumption
J Zedlewski, S Sobti, N Garg, F Zheng, A Krishnamurthy, R Wang
2nd USENIX Conference on File and Storage Technologies (FAST 03), 2003
3082003
Mechanism for scheduling execution of threads for fair resource allocation in a multi-threaded and/or multi-core processing system
JR Zedlewski, CA Waldspurger
US Patent 7,707,578, 2010
1912010
Method and system for determining a cost-benefit metric for potential virtual machine migrations
M Ji, CA Waldspurger, J Zedlewski
US Patent 8,095,929, 2012
1512012
Dynamic verification of validity of executable code
CA Waldspurger, O Agesen, X Chen, JR Zedlewski, T Garfinkel
US Patent 7,984,304, 2011
1432011
Utilizing cache information to manage memory access and cache utilization
J Zedlewski, C Waldspurger
US Patent 7,831,773, 2010
1332010
Utilizing cache information to manage memory access and cache utilization
J Zedlewski, C Waldspurger
US Patent 7,434,002, 2008
912008
Method and system for improving the accuracy of timing and process accounting within virtual machines
C Waldspurger, M Craig, R Dharan, RS Kambo, TP Mann, SA Muckle, ...
US Patent 7,945,908, 2011
872011
Use of dynamic entitlement and adaptive threshold for cluster process balancing
M Ji, CA Waldspurger, JR Zedlewski
US Patent 8,667,500, 2014
342014
Scheduling selected contexts in response to detecting skew between coscheduled contexts
C Waldspurger, J Zedlewski, A Dorofeev
US Patent 8,127,301, 2012
142012
Defining and measuring skew between coscheduled contexts
C Waldspurger, J Zedlewski, A Dorofeev
US Patent 8,296,767, 2012
132012
Alternating scheduling and descheduling of coscheduled contexts
C Waldspurger, J Zedlewski, A Dorofeev
US Patent 8,171,488, 2012
102012
Detecting and responding to skew between coscheduled contexts
C Waldspurger, J Zedlewski, A Dorofeev
US Patent 8,176,493, 2012
62012
Mechanism for scheduling execution of threads for fair resource allocation in a multi-threaded and/or multi-core processing system
JR Zedlewski, CA Waldspurger
US Patent 10,417,048, 2019
2019
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